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1 ? fn7465.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl29002 light-to-digital i 2 c sensor the isl29002 is an integrated light sensor with a built-in integrating type adc and a standard i 2 c interface. the device transforms illuminance, ambient light level in lux, into a digital output signal accessible through i 2 c. the sensor precisely converts illuminance from 1lux to 100,000lux. the adc features up to 15-bit effe ctive resolution. the sensor includes another photodiode covered with metal to reduce the effects of dark output readi ng that may be significant in low lux levels. the isl29002 can control display panel backlighting depending on ambient light conditions, addi ng artificial intelligence by approximating the response of a human eye. the isl29002 can also manage portable peripheral illumination based upon lighting conditions ex tending battery life. in normal operation, the isl29002 consumes less than 300a of supply current. a software power down mode is controlled via the i 2 c interface and disables all but the i 2 c interface. the supply current is then reduced to less than 88a. designed to operate on supplies from 2.5v to 3.3v, the isl29002 is specified for opera tion over the -40c to +85c ambient temperature range. it is packaged in a clear, pb-free 8 ld odfn package. block diagram features ?i 2 c interface fast mode at 400khz ? 88a disabled current ? adjustable max lux range: 10,000lux to 100,000lux ? up to 15-bit effective resolution ? adjustable resolution: 0.15 to 1.65 counts per lux ? simple output code proportional to lux ? flicker/noise rejection ? variable integration time; 50ms to 550ms ? 2.5v to 3.3v supply ? 8 ld odfn (3mmx3mm) ? temperature compensation ? pb-free available (rohs compliant) applications ? backlight sensing ? automatic backlight adjustment ? backlight linearity adjustments pinout isl29002 (8 ld odfn) top view vdd r ext gnd a1 a2 a0 sda scl command register integrating adc data register i 2 c photodiode 1 photodiode2 mux 3 2 6 5 4 7 8 1 fosc iref counter 2 16 ordering information part number (note) temp. range (c) tape & reel package (pb-free) pkg. dwg. # isl29002iroz -40 to +85 - 8 ld 3x3 odfn mdp0052 isl29002iroz-t7 -40 to +85 7? 8 ld 3x3 odfn mdp0052 note: intersil pb-free odfn products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 2 3 4 8 7 6 5 vdd gnd r ext a0 sda scl a2 a1 thermal pad data sheet december 1, 2006
2 fn7465.2 december 1, 2006 absolute maxi mum ratings (t a = +25c) maximum supply voltage between v dd and gnd . . . . . . . . . . 3.6v i 2 c address pin voltage (a2, a1, a0) . . . . . . . . . . . . . -0.2v to 3.6v i 2 c bus pin voltage (scl, sda) . . . . . . . . . . . . . . . . . -0.2v to 5.5v i 2 c bus pin current (scl, sda) . . . . . . . . . . . . . . . . . . . . . . <10ma r ext pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 3.6v operating temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-45c to +100c esd, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v dd = 3v, t a = +25c, r ext = 100k 1%, i 2 c command = 00(hex) (note 1), unless otherwise specified. parameter description condition min typ max unit v dd power supply range 2.25 3.63 v i dd supply current 0.3 0.375 ma i dd1 supply current software disabled 88 110 a t upd internal update time/conversion time 85 110 135 ms f osc internal oscillator frequency 300 khz f i2c i 2 c clock rate (note 2) 1 400 khz data0 dark adc code e = 0lux e = 0lux, integration time = 550ms 4 1 counts data1 adc code adc full scale count value 32,768 counts data2 adc code e = 25,000lux, fluorescent light (note 3) 13,500 16,000 18,500 counts v ref voltage of r ext pin 0.45 0.51 0.53 v v tl scl, sda, a0, a1, and a2 threshold lo (note 4) 1.05 v v th scl, sda, a0, a1, and a2 threshold hi (note 4) 1.95 v i sda sda current sinking capability 3 5 ma i il a0, a1, and a2 input current lo a0 = a1 = a2 = gnd 0.1 a i ih a0, a1, and a2 input current hi a0 = a1 = a2 = v dd 0.1 a notes: 1. for i 2 c command = 00h, the adc converts the current of (photo) diode 1 into a 16 bit data with an internally timed integration of 110 ms for r ext = 100k , 1% tolerance. 2. minimum i 2 c clock rate is guaranteed by design. 3. fluorescent light is substi tuted by an led at production. 4. the voltage threshold levels of the sda and scl pins are vdd dependent: v tl = 0.35*v dd . v th = 0.65*v dd . isl29002
3 fn7465.2 december 1, 2006 pin descriptions pin number pin name description 1 vdd positive supply. connect to a clean 2.25v to 3.3v supply 2 gnd ground. the thermal pad is connected to the gnd pin 3r ext external resistor pin is for the a dc reference current, the integration time adjustment in internal timing mode, and lux range/resolution adjustment. 100k 1% tolerance resistor recommended. 4 a0 bit 0 of the i 2 c address. the address pins have an open gate equivalent circuit. these are the least-significant bits of the i 2 c address. the eight possible addresses are 40(hex) through 48(hex). 5 a1 bit 1 of the i 2 c address. 6 a2 bit 2 of the i 2 c address. 7scli 2 c serial clock line the i 2 c bus lines can pulled above v dd , 5.5v max. 8sdai 2 c serial data line typical performance curves r ext = 100k figure 1. supply current vs supply voltage fig ure 2. output code for 0lux vs supply voltage figure 3. output code vs supply voltage fig ure 4. oscillator frequency vs supply voltage 2.0 2.3 2.6 2.9 3.2 3.5 3.8 320 306 292 278 264 250 supply current ( a) supply voltage (v) t a = 27 o c command = 00h 25000 lux 1000 lux t a = +27c command = 00h 2.0 2.3 2.6 2.9 3.2 3.5 3.8 10 8 6 4 2 0 output code (counts) supply voltage (v) t a = 27 o c command = 00h 0 lux t a = +27c command = 00h 0 lux 2.0 2.3 2.6 2.9 3.2 3.5 3.8 1.015 1.010 1.005 1.000 0.995 0.990 output code ratio (% from 3v) supply voltage (v) t a = 27 o c command = 00h 25000 lux 1000 lux t a = +27c command = 00h 2.0 2.3 2.6 2.9 3.2 3.5 3.8 320.0 319.5 319.0 318.5 318.0 oscillator frequency (khz) supply voltage (v) t a = 27 o c t a = +27c isl29002
4 fn7465.2 december 1, 2006 figure 5. supply current vs temperature figure 6. output code for 0lux vs temperature figure 7. output code vs temperature figure 8. oscillator frequency vs temperature figure 9. relative intensity figure 10. radiation pattern typical performance curves r ext = 100k (continued) -60 -20 20 60 100 315 305 295 285 275 265 supply current ( a) temperature ( o c) v dd = 3v command = 00h 25000 lux 1000 lux -60 -20 20 60 100 10 8 6 4 2 0 output code (counts) temperature ( o c) v dd = 3v command = 00h 0 lux -60 -20 20 60 100 1.080 1.048 1.016 0.984 0.952 0.920 output code ratio (% from 25 o c) temperature ( o c) v dd = 3v command = 00h 25000 lux 1000 lux -60 -20 20 60 100 330 329 328 327 326 325 oscillator frequency (khz) temperature ( o c) v dd = 3v 0 20 40 60 80 100 300 400 500 600 700 800 900 1000 1100 wavelength (nm) normalized response (%) k = 7.5 n = 1.85 human visibility cie standard d1 normalized n(d1-kd2) normalized d2 normalized radiation pattern luminosity angle relative sensitivity isl29002
5 fn7465.2 december 1, 2006 principles of operation photodiodes and adc the isl29002 contains two photodiodes. one of the photodiodes is sensitive to visi ble and infrared light (diode 1). another photodiode (diode 2) is covered with metal and can be used to cancel the effects of dark output code, the unwanted number of counts in the absence of light. diode 2 can also be used to cancel the presence of ir. see ir rejection in the applications section. the isl290 02 also contains an on-chip integrating analog-to-digital converter (adc) to convert photodiode currents into digital data. the interface to the adc is implemented using the standard i 2 c interface. the isl29002?s built-in adc is a charge-balancing integrating converter type. the integrating adc converts the photodiode current to frequency. the repetition rate is then counted by a binary counter to output a digital code - number of counts. the isl29002 can be configured (in external timing mode) to output a maximum 2 16 (65,536) counts. the adc has two timing controls, internal timing and external timing. with internal timing, the number of clock cycles per integration time is fixed at 2 15 (32,726), hence the number of counts is limited to 2 15 (32,7268). with external timing, the user have the flexibility to vary the maximum number of counts up to 2 16 (65,536). in addition, the adc has three operating modes (please consult table 1 for a complete list of modes.) in the first operating mode, the adc only integrates diode 1's current. in the second operating mode, the adc only integr ates the other diode, diode 2?s current. both operating mode 1 and mode 2 has a 16-bit unsigned-magnitude format. in the third operating mode, the adc integrates diode 2's current first, then diode 1's current. in this mode, the output is a 16-bit 2?s complement format. the total integration time is doubled, and the digital output is the difference of the two photodiode currents (diode 1?s current minus diode 2?s current). any of the three operating modes can be used with either of the two timing controls, either internally or externally controlled integration timing. i 2 c interface the isl29002 contains a single 8-bit command register that can be written via the i 2 c interface. the command register defines the operation of the device, which does not change until the command register is overwritten. the isl29002 contains four 8-bit data registers that can be read via the i 2 c interface. the first two data registers contain the adc's latest digital output, while the second two registers contain the number of clock cycles in the previous integration period. the isl29002?s i 2 c address is pin-selectable by pins a0, a1, and a2. these pins can be tied or driven either high or low. they comprise the least-significant three bits of the i 2 c address, while the four most-significant bits are hardwired as 1000. the eight possible addresses are therefore 40h through 47h. figure 11b shows a sample one-byte read. (a typical application will read two to four bytes, however.) the i 2 c bus master always drives the scl (c lock) line, while either the master or the slave can drive the sda (data) line. every i 2 c transaction begins with the mast er asserting a start condition (sda falling while scl remains high). the following byte is driven by the master, and includes the slave address and read/write bit. the receiving device is responsible for pulling sda low during the acknowledgement period. any writes to the isl29002 overwrite the command register, changing the device?s mode. any reads from the isl29002 return two or four bytes of sensor data and counter value, depending upon the operating mode. neither the command register nor the data registers have internal addresses, and none of the registers can be individually addressed. every i 2 c transaction ends with th e master asserting a stop condition (sda rising while scl remains high). i 2 c transaction flow to write, the master sends sl ave address 44(hex) plus the write bit. then master sends the adc command to the device which defines its operation. as soon as the isl29002 receives the adc command, it will execute and then store the readings in the register after the analog-to-digital conversion is complete. while the isl29002 is executing the command and also after the execution, the i 2 c bus is available for transactions other than the isl29002. after command execution, sensor dat a readings are stored in the registers. note that if a read is received before the execution is finished, the data retrieved is previous data sensor reading. typical integrat ion/conversion time is 100ms (for r ext = 100k and internal timing mode). it is recommended that a read is sent 120ms later because the fosc variation is 20%. the operation of the device does not change until the command register is overwritten. hence, when the master sends a slave address 44(hex) and a write bit, the isl29002 will repeat the same command from the previous write transaction. to read, master sends slave address 44(hex) plus the read bit. then isl29002 will hold the sda line to send data to master. note that the master need not send an address register to access the data. as soon as the isl29002 receives the read bit. it will send 4 bytes. the 1st byte is the lsb of the sensor reading. the 2nd byte is the msb of the sensor reading. the 3rd byte is lsb of the counter reading. the 4th byte is the msb of the counter reading. if inter nal timing mode is selected, only the 1st and 2nd data byte are necessary; the master can assert a stop after the 2nd data byte is received. for more information about the i 2 c standard, please consult the philips ? i 2 c specification documents. isl29002
6 fn7465.2 december 1, 2006 command register the command register is used to define the adc's operations. table 1 shows the primary commands used to control the adc. note that there are two classes of operating commands: three for internal timing, and three for external (arbitrary) timing. when using any of the three internal timing commands, the device self-times each conversi on, which is nominally 110ms (with r ext = 100k ). when using any of the three external timing commands, each command received by the device ends one conversion and begins another. the integration time of the device is thus the time between one i 2 c external timing command and the next. the integration time can be between 1ms and 100ms. the external timing commands can be used to synchronize the adc?s integrating time to a pwm dimming frequency in a backlight system in order to eliminate noise. table 1. command registers and functions command function 8c(hex) adc is powered-down. to enable adc from a powered-down state, send any command to the isl29002. 0c(hex) adc is reset. a reset restarts the counter value to zero and returns the clock cycle to zero. 00(hex) internal timing mode. integration time is 110ms per photodiode. adc converts diode 1?s current (i diode1 ) into an unsigned-magnitude 16-bit data. 04(hex) adc converts diode 2?s current (i diode2 ) into unsigned-magnitude 16-bit data. 08(hex) adc converts i diode1 -i diode2 into 2?s-complement 16-bit data. 30(hex) external timing mode. each external timing command sent to the device ends one integration period and begins another. adc converts diode 1?s current (i diode1 ) into unsigned-magnitude 16-bit data. 34(hex) adc converts diode 2?s current (i diode1 ) into unsigned-magnitude 16-bit data. 38(hex) adc converts i diode1 -i diode2 into 2?s-complement 16-bit data. 1xxx_xxxx (binary) i 2 c communication test. the value written to the command register can be read back via the i 2 c bus. figure 11a. i 2 c write timing diagram sample figure 11b. i 2 c read timing diagram sample figure 11. start w aa a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a aa 123456789123456789 stop sda driven by master power down cmd 8c(h) i 2 c clk in sda driven by master i 2 c sda in i 2 c sda out device address 40(h) to 47(h) i 2 c data start a a a6 a5 a4 a3 a2 a1 a0 r a a a a d7 d6 d5 d4 d3 d2 d1 d0 a d7 d6 d5 d4 d3 d2 d1 d0 a 123456789123456789123456789 i 2 c clk in sda driven by master r/w sda driven by isl29002 i 2 c sda in i 2 c sda out device address 44(hex) i 2 c data msb of sensor reading stop lsb of sensor reading sda driven by isl29002 isl29002
7 fn7465.2 december 1, 2006 data registers the isl29002 contains four 8-bit data registers. these registers cannot be specifically addressed, as is conventional with other i 2 c peripherals; instead, performing a read operation on the device always returns all available registers in ascending order. see table 2 for a description of each register. the first two 8-bit data registers contain the most recent sensor reading. the meaning of the specific value stored in these data registers depends on the command written via the i 2 c interface; see table 1 for information on the various commands. the first byte read over the i 2 c interface is the least-significant byte; the second is the most significant. this byte ordering is often called ?little-endian? ordering. the third and fourth 8-bit data registers contain the integration counter value corresponding to the most recent sensor reading. the isl29002 includes a free-running oscillator, each cycle of which increments a 16-bit counter. at the end of each integration peri od, the value of this counter is made available in these two 8-bit registers. like the sensor reading, the integrati on counter value is read across the i 2 c bus in little-endian order. note that the integration counter value is only available when using one of the thr ee externally-timed operating modes; when using internally-timed modes, the device will nak after the two-byte sensor reading has been read. internal timing mode when using one of the three internal timing modes, each integration period of the isl29002 is timed by 2 15 = 32,768 clock cycles of an internal oscillator. the nominal frequency of the internal oscillator is 300khz, which provides 110ms internally-timed integration periods. the oscillator frequency is dependent upon an external resistor, r ext , and can be adjusted by selecting a different resistor value. the resolution and maximum range of the device are also affected by changes in r ext ; see below. the oscillator frequency, f osc can be calculated with the following equation: r ext is an external resistor required nominally 100k , and provides 110ms internal timing and a 1-50,000lux range for diode 1. doubling this resistor value to 200k halves the internal oscillator frequency, providing 220ms internal timing. in addition, the maximum lux range of diode 1 is also halved, from 50,000lux to 25,000 lux, and the resolution is doubled, from 0.65 counts per lux to 1.3 counts per lux. the acceptable range of this resistor is 50k (providing 55ms internal timing, 100,000lux maximum reading, ~0.33 counts per lux) to 500k (550ms internal timing, 10,000lux maximum reading, ~3.3 counts per lux). see table 3 for r ext selection . when using one of the three internal timing modes, the isl29002?s resolution is determined by the ratio of the max lux range to 32,768, the number of clock cycles per integration. the following equations describe t he light intensity, e in lux, as a function of the sensor re ading, and the integration time as a function of the external resistor. where, e is the measured light intensity in lux data1 is the sensor reading t int is the integration time, r ext is external resistor value. external timing mode when using one of the three external timing modes, each integration period of the isl29002 is determined by the time which passes between consecutive external timing commands received over the i 2 c bus. the user starts the integration by sending an external command and stops the integration by sending another external comm and. the integration time, t int , therefore is determined by the following equation: where: i i2c is the number of i 2 c clock cycles to obtain the t int. f i2c is the i 2 c operating frequency. the internal oscillator, f osc , operates identically in both the internal and external timing modes, with the same dependence on r ext . however, when using one of the three external timing modes, the number of clock cycles per table 2. data registers address contents 00(hex) least-significant byte of most recent sensor reading. 01(hex) most-significant byte of most recent sensor reading. 02(hex) least-significant byte of integration counter value corresponding to most recent sensor reading. 03(hex) most-significant byte of integration counter value corresponding to most recent sensor reading. f osc 300khz 100k r ext ------------------ ? = (eq. 1) table 3. r ext resistor selection guide r ext (k ) integration time (ms) lux range (lux) resolution, counts/lux 50 (min) 55 100,000 0.33 90.9 100 55,000 0.61 100 recommended 110 50,000 0.67 200 220 25,000 1.33 500 (max) 550 10,000 3.33 e lux () 1 32,768 ----------------- - = 50 000lux , r ext 100k ? () --------------------------------------- data1 ?? (eq. 2) tint 110ms r ext 100k ------------------ ? = (eq. 3) t int i i2c f i2c ---------- = (eq. 4) isl29002
8 fn7465.2 december 1, 2006 integration is no longer fixed at 32,768, but varies with the chosen integration time, and is limited to 65,536. in order to avoid erroneous lux readings the integration must be short enough not to allow an overflow in the counter register. where: t int = user defined integration time f osc = 300khz*100k /r ext . isl29002?s internal oscillator. not to be confused with the i 2 c?s frequency. r ext = user defined external resistor to adjust f osc . 100k recommended. the number of clock cycles in the previous in tegration period is provided in the third and f ourth bytes of data read across the i 2 c bus. this two-byte value is called the integration counter value. when using one of the three external timing modes, the isl29002?s resolution varies with the integration time. the resolution is determined by the ratio of the max lux range to the number of clock cycles per integration. the following equations describe the light intensity as a function of sensor reading, in tegration counter value, and integration time: t int = time interval between external time commands where l is the measured light intensity, data1 is the sensor reading, data2 is the integrat ion counter value, t is the integration time, and r ext is external resistor value. noise rejection and integration time in general, integrating type adc?s have an excellent noise- rejection characteristics for periodic noise sources whose frequency is an integer multiple of the integration time. for instance, a 60hz ac unwanted signal?s sum from 0ms to n*16.66ms (n = 1,2...n i ) is zero. similarly, setting the isl29002?s integration time to an integer multiple of periodic noise signal greatly improves th e light sensor output signal in the presence of noise. the integration time, t int , of the isl29002 is set by an external resistor r ext . see equation 3. design example 1 using the isl29002, determine a suitable integration time, t int , that will ignore the presen ce of both 60hz and 50hz noise. accordingly, specify the r ext value. given that the i 2 c clock is at f i2c = 10khz. solution 1 - using internal timing t int = n(1/60hz) = m(1/50hz). in order to achieve both 60hz and 50hz ac rejection, the in tegration time needs to be adjusted to coincide with an integer multiple of the ac noise cycle times. n/m = 60hz/50hz = 6/5. the first instance of integer values at which t int rejects both 60hz and 50hz is when m = 5, and n = 6. t int = 6(1/60hz) = 5(1/50hz) = 100ms from equation 3: r ext = t int * (100k /110ms) = 90.9k . by populating r ext =90k , the isl29002 defaults to 100ms integration time and will reject the presence of both 60hz and 50hz power line signals. solution 2 - using external timing from solution 1, the desired integration time is 100ms. note that the r ext resistor does not determine the integration time when using external timing mode. instead, the integration and the 16-bit counter starts when an external timing mode command is sent and end when another external timing mode is sent. in other words, the time between two external timing mode command is the integr ation time. th e programmer determines how many clock cycles to wait between two external timing commands. i i2c = f i2c * t int , where i i2c = number of i 2 c cycles i i2c = 10khz * 100ms i i2c = 1,000 i 2 c clock cycles. an exte rnal timing command 1,000 cycles after another external timing command rejects both 60hz and 50hz ac noise signals. ir rejection any filament type light source has a high presence of infrared component invisible to the human eye. a white fluorescent lamp, on the other hand has a low ir content. as a result, output sensitivity may vary depending on the light source. maximum attenuation of ir can be achieved by properly scaling the readings of diode1 and diode2. the user obtains data reading from sensor diode 1, d1 , which is sensitive to visible and ir, then reading from sensor diode 2, d2 which is mostly sensitive from ir. the graph on figure 9 shows the effective spectral response after applying equation 7 of the isl29002 from 400nm to 1000nm. the equation below describes the method of cancelling ir in internal timing mode. where: data = lux amount in number of counts less ir presence d1 = data reading of diode 1 d2 = data reading of diode 2 n = 1.85. this is a fudge factor to scale back the sensitivity up to ensure equation 2 is valid. k = 7.5. this is a scaling factor for the ir sensitive diode 2. t int 65,536 f osc ----------------- - < (eq. 5) elux () 50 000lux , r ext 100k ? () ------------------------------------------ - data1 data2 ----------------- ? = (eq. 6) d3 n d1 kd2 ? () = (eq. 7) isl29002
9 fn7465.2 december 1, 2006 typical circuit a typical application circuit is shown in figure 12. suggested pcb footprint see figure 13. footprint pads should be a nominal 1-to-1 correspondence with package pads. the large, exposed central die-mounting paddle in the center of the package requires neither thermal nor electrical connection to the pcb, and such connection should be avoided. layout considerations the isl29002 is relatively insensitive to layout. like other i 2 c devices, it is intended to provide excellent performance even in significantly noisy environments. there are only a few considerations that will ensure best performance. route the supply and i 2 c traces as far as possible from all sources of noise. use two power-supply decoupling capacitors, 4.7f and 0.1f, placed close to the device. soldering considerations convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. the isl29002?s plastic odfn package does not require a custom reflow soldering profile, and is qualified to +260c. a standard reflow soldering profile with a +260c maximum is recommended. special handling odfn8 is rated as jedec moisture level 4. standard jedec level 4 procedure should be followed: 72hr floor life at less than +30c 60% rh. when baking the device, the temperature required is +110c or less due to special molding compound. isl29002 vdd vss rext a0 a1 a2 sda scl + 4.7 f 0.1f 100k microcontroller sda scl 2.5- 3.3v figure 12. typical circuit figure 13. suggested pcb footprint (6x0.65) (2.80 typ) (1.40) (2.29) (8x0.60) (8x0.30) isl29002
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7465.2 december 1, 2006 isl29002 optical dual flat no-lead family (odfn) top view 12 3 54 4 2x 0.10 c 2x 0.10 c a b typ. 1 2 3 46 (e2) (d2) pin bottom view 3 2 6 1 8 4 5 7 6 ld odfn 8 ld odfn detail x plane seating (all leads 0.08 c & exposed pad) 0.10 c side view see (c) a a1 d a 0.10 c e b 5 #1 i.d. 3 3 l b bottom view (2.0x2.1 body) 0.10 c a b b (3.0x3.0 body) (d2) 3 pin #1 i.d. typ. l e1 e (e2) 3 detail "x" e c c 2 e1 0.10 c a b typ. 1 2 3 45 (e2) (d2) pin 5 ld odfn #1 i.d. 3 3 l b bottom view (2.0x2.1 body) e e1 5 mdp0052 optical dual flat no-lead family symbol odfn5 odfn6 odfn8 tolerance note a 0.70 0.70 0.70 0.05 a1 0.02 0.02 0.02 +0.03/-0.02 b 0.30 0.30 0.30 0.05 c 0.20 0.20 0.20 reference 2 d 2.00 2.00 3.00 basic d2 1.35 1.35 2.29 reference 3 e 2.10 2.10 3.00 basic e2 0.65 0.65 1.40 reference 3 e 0.65 0.65 0.65 basic e1 1.30 1.30 1.95 basic l 0.35 0.35 0.40 0.05 rev. 4 5/06 notes: 1. dimensioning and tolerancing per asme y14.5m - 1994. 2. exposed lead at side of package is a non-functional feature. 3. dimension d2 and e2 define the size of the exposed pad. 4. odfn 5 ld version has no cent er lead (shown as dashed line).
isl29002 printer friendly version light-to-digital i 2 c sensor datasheets, related docs & simulations description key features parametric data application diagrams related devices ordering information part no. design-in status temp. package msl price us $ isl29002iroz active ind 8 ld dfn 4op 1.35 isl29002iroz-evalz active eval board n/a isl29002iroz-t7 active ind 8 ld dfn t+r 4op 1.35 isl29002croz inactive comm 8 ld dfn 4op isl29002croz-eval inactive eval board n/a isl29002croz-evalz inactive eval board n/a ISL29002CROZ-T7 inactive comm 8 ld dfn t+r 4op the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the isl29002 is an integrated light sensor with a built-in integrating type adc and a standard i 2 c interface. the device transforms illuminance, ambient light level in lux, into a digital output signal accessible through i 2 c. the sensor precisely converts illuminance from 1lux to 100,000lux. the adc features up to 15-bit effective resolution. the sensor includes another photodiode covered with metal to reduce the effects of dark output reading that may be significant in low lux levels. the isl29002 can control display panel backlighting depending on ambient light conditions, adding artificial intelligence by approximating the response of a human eye. the isl29002 can also manage portable peripheral illumination based upon lighting conditions extending battery life. in normal operation, the isl29002 consumes less than 300 a of supply current. a software power down mode is controlled via the i 2 c interface and disables all but the i 2 c interface. the supply current is then reduced to less than 88 a. designed to operate on supplies from 2.5v to 3.3v, the isl29002 is specified for operation over the -40c to +85c ambient temperature range. it is packaged in a clear, pb-free 8 ld odfn package. key f eatures i 2 c interface fast mode at 400khz 88 a disabled current adjustable max lux range: 10,000lux to 100,000lux up to 15-bit effective resolution adjustable resolution: 0.15 to 1.65 counts per lux simple output code proportional to lux flicker/noise rejection variable integration time; 50ms to 550ms 2.5v to 3.3v supply 8 ld odfn (3mmx3mm) temperature compensation pb-free available (rohs compliant) related documentation
datasheet(s): light-to-digital i 2 c sensor technical homepage: display products parametric data peak sensitivity (nm) 550 v s (min) (v) 2.25 v s (max) (v) 3.63 supply current ( a) 300 resolution (bits) 15 lux range (max) (lux) 100000 counts per lux (max) (counts) 1.65 dark adc code @ e v = 0lux (max) (count) 1 gain selection? n output interface i 2 c address selection pins? y enable pin? n package dimensions (mm) 3.0x3.0x0.7 application block diagrams automated external defibrillator digital projector digital still camera handheld/portable display (lcd/oled) lcd-tv panel large lcd panel (14 to 24 inch) mp3 player security cctv small/medium lcd panel (less than 14 inch) video poker applications backlight sensing automatic backlight adjustment backlight linearity adjustments related devices parametric table isl29001 light-to-digital sensor isl29003 light-to-digital output sensor with high sensitivity, gain selection, interrupt function and i 2 c interface isl29004 light-to-digital output sensor with address selection, high sensitivity, gain selection, interrupt function and i 2 c interface about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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